1. Field of the Invention
The present invention generally relates to semiconductor integrated circuits, and particularly relates to a semiconductor integrated circuit having dummy patterns.
2. Description of the Related Art
When a semiconductor integrated circuit of a large scale is to be manufactured, the density of circuit wires may vary from position to position on the substrate. If this happens, optimum etching conditions vary depending on the positions, so that the etching processing will have varying effects. At the positions where the wire density is small, a resist pattern may disappear, resulting in a severance of a wire, or resulting in a thinning of the wire width that will dramatically increase the wire resistance. If the thinning of the wire is significant, the wire may fall down as a result of such thinning. In order to avoid these defectives, semiconductor integrated circuits of today have wire dummies arranged at positions of small wire densities, thereby insuring a constant wire density allover the substrate.
FIG. 1 is a plan view showing a portion of a semiconductor integrated circuit having a constant wire density created by wire dummies.
FIG. 1 shows a plan view of wires provided at the nth layer on a semiconductor substrate. Wires 10 through 12 of the nth layer are arranged as circuit wires (n is a positive integer). There is no circuit wire between the wires 10 and 11, so that the severance or thinning of wires may develop if the semiconductor integrated circuit is manufactured by etching processes without taking any counter measures. In order to avoid this, as shown in FIG. 1, a circuit is designed such that wire dummies 13 are arranged in the blank area between the wires of the nth layer. These wire dummies 13 are not electrically connected to the circuit, but are provided merely for the purpose of achieving a constant wire density and constant etching conditions.
The arrangement of the wire dummies 13 makes it possible to avoid the severance and thinning of wires caused by varying etching conditions.
The wire dummies 13 do not have any direct electrical connection with the real circuitry, but create undesirable capacitance.
FIG. 2 is a drawing for explaining the generation of capacitance by the wire dummies 13.
As shown in FIG. 2, the n+1th layer atop the nth layer has wires 14 and 15 arranges as part of the real circuitry, and the n−1th layer beneath the nth layer has wires 16 and 17 arranged as part of the real circuitry. Capacitance comes into existence between the wires 14 through 17 and the wire dummies 13.
FIG. 3 is a drawing for explaining the effect of capacitance by the wire dummies 13.
On the left-hand side in FIG. 3, a cross-sectional view taken along the line A–A′ in FIG. 2 is shown. On the right-hand side in FIG. 3, a illustrative drawing is shown to demonstrate a coupling capacitance that develops at a position encircled by a dotted circle in the cross-sectional view. As shown in these illustrations, capacitances C1 and C2 are generated between the wires 14 and 15 and a wire dummy 13. When a circuit simulation is conducted as part of the circuit designing process, wires of the real circuitry can be incorporated into the simulation by identifying the capacitance between the wire. The wire dummies 13, however, are automatically generated after the circuit designing process. Because of this, the capacitances C1 and C2 between the wires and the wire dummy 13 cannot be identified and incorporated into the simulation. As a result, these capacitances surface as simulation errors, thereby degrading the accuracy of simulation analysis.
In the method of generating related-art wire dummy patterns, unit dummy patterns each having a constant size and a constant shape are arranged at predetermined intervals to fill a blank area where no wires are present. According to this method, however, no dummy pattern is inserted at areas where the interval between wires is smaller than the size of the dummy pattern. If the interval between wires is wider, a single row of dummy patterns may be inserted. Even when the wire interval is further widened, however, only a single row of dummy patterns may be arranged if the wire interval is not sufficient to accommodate the second row of dummy patterns while keeping the predetermined interval with the first row. In this manner, if the dummy patterns having the predetermined size are to be arranged at the predetermined intervals, the arrangement of dummy patterns exhibits stepped, discreet changes whereas the wire interval exhibits a gradual, continuous change. Because of this, a blank area is likely to be generated, resulting in a failure to increase the area of resist patterns and a failure to achieve a constant area ratio for the resist patterns.
Accordingly, there is a need for a semiconductor integrated circuit which has a reduced capacitance between wires of the real circuitry and wire dummies, thereby improving the accuracy of simulation analysis.
Further, there is a need for a semiconductor integrated circuit which has dummy patterns arranged therein such as to increase the area ratio of resist patterns and to make the area ratio constant regardless of the length of wire intervals.